Semiconductor Engineering

Heterogeneous NPU Data Movement: What The Execution Flow Shows

Heterogeneous NPU designs bring together multiple specialized compute engines to support the range of operators required by ...
IEEE

Optimizing High-Level Synthesis Sparse Matrix-Vector Kernel for Alveo FPGAs

Abstract: Sparse matrix-vector multiplication (SpMV) is a critical kernel in scientific computing and high-performance applications, yet it remains challenging to optimize due to irregular memory ...
GitHub

Systolic-Processor-Architecture /DPU_array_matrix_multiplication_3

DPU0: DPU_matrix_multiplication port map(A0,B0,CLK,clear,S03,S01,O0); DPU1: DPU_matrix_multiplication port map(A1,S01,CLK,clear,S14,S12,O1); DPU2: DPU_matrix ...
IEEE

ReSpar: Reordering Algorithm for ReRAM-based Sparse Matrix-Vector Multiplication Accelerator

Abstract: Sparse matrix-vector multiplication (SpMV) serves as a crucial operation for several key application domains, such as graph analytics and scientific computing, in the era of big data. The ...