Samsung Electronics has concretized its 2-nanometer (nm; 1 nm = one billionth of a meter) foundry process roadmap. It announced plans to expand mass production to mobile in 2025, high-performance ...
TL;DR: Samsung Foundry aims to lead the advanced semiconductor market by improving its 2nm process yield to 70% within 2024, crucial for securing major US clients like Qualcomm and competing with TSMC ...
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Intel Foundry boss leaves for Qualcomm — Naga Chandrasekaran takes charge of the unit
Naga Chandrasekaran promoted to Chief Technology and Operations Officer as well as the general manager of Intel Foundry responsible for development of advanced process technologies and day-to-day ...
The South Korean giant has plans to unveil its next-gen 1nm process node schedule at the Foundry Forum & SAFE Forum 2024, which will be held in the US between June 12-13, according to Korean media. It ...
Lip-Bu Tan, the chief executive of Intel, is considering stopping the promotion of the company's 18A fabrication technology (1.8nm-class) to foundry customers, instead shifting the company's efforts ...
Intel announces expanded process roadmap, customers and ecosystem partners to deliver on ambition to be the No. 2 foundry by 2030. Intel also announced the addition of Intel Foundry FCBGA 2D+ to its ...
DEEPX Signs 2nm Process Agreement with Samsung Foundry for Next-Generation AI Chip DX-M2 DEEPX has signed a 2nm process development agreement with Samsung Foundry to develop the world’s first ...
Zarlink Semiconductor today introduced a commercial foundry service for producing analog chips. Using Zarlink’s high-voltage, high-speed process, the foundry service is aimed at building chips for ...
Samsung announced a comprehensive foundry process technology roadmap to 8nm, 7nm, 6nm, 5nm, 4nm and 18nm FD-SOI in its newest process technology roadmap. “The ubiquitous nature of smart, connected ...
The Fabless Semiconductor Association (FSA) and JEDEC today released the Foundry Process Qualification Guideline describing a minimum set of requirements to qualify a new semiconductor wafer process.
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