Semiconductor Engineering

Reusable UPF: Transitioning From RTL To Gate Level Verification

This paper highlights the differences between an RTL UPF and a Gate Level Simulation UPF, and presents a new methodology to write RTL UPF in such a way that minimal changes are required during ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...
EDN

SunaptiCAD VeriLogger Extreme: Verilog 2001 simulator provides faster RTL and gate-level simulations

Reducing simulation debugging time, the compiled-code Verilogger Extreme Verilog 2001 simulator provides fast simulation of RTL and gate-level simulations using SDF (Synopsys Delay Format) timing ...
Semiconductor Engineering

Simulation: Go Parallel Or Go Home

Although complemented by other valuable technologies, functional simulation remains at the heart of semiconductor verification. Every chip project still develops a testbench, usually compliant with ...
Business Insider

Cadence Launches Xcelium Parallel Simulator, the Industry's First Production-Proven Parallel Simulator

Delivers third generation of simulation with multi-core parallel computing as part of the industry-leading Cadence Verification Suite Provides an average 2X improved single-core performance Offers an ...
EDN

Calypto Delivers Industry’s First RTL Power Analyzer Based on Sequential Analysis Technology

SANTA CLARA, Calif. –– August 24, 2009 –– Calypto® Design Systems Inc. (www.calypto.com) today announced it has developed the industry’s most accurate register-transfer level (RTL) power analysis ...