Business Wire

Cadence Demonstrates IP Test Silicon for PCI Express 6.0 Specification on TSMC N5 Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the immediate availability of Cadence ® IP supporting the PCI Express ® (PCIe ®) 6.0 specification on the ...
Business Wire

Cadence and NVIDIA Unveil Groundbreaking Generative AI and Accelerated Compute-Driven Innovations

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced an expansion of its multi-year collaboration with NVIDIA across EDA, system design and analysis, digital ...
EDN

Cadence Delivers Full-Chip Test Technology

Cadence Design Systems has announced Cadence Encounter Test Architect, a full-chip test architecture development product. It includes a unified compiler-based methodology for full-chip test to provide ...
Electronic Design

Imec Teams With Cadence on DFT Solution for 3-D Memory-on-Logic

January 25, 2013. At the European 3D TSV Summit in Grenoble, France, on January 22-23, 2013, imec announced that together with Cadence Design Systems they have developed, implemented, and validated an ...
EDN

Cadence buys IBM’s design-for-test tools business

SAN MATEO, Calif. — Bolstering its position as the EDA industry's leading supplier, Cadence Design Systems Inc. has purchased the design-for-test technology and group personnel of IBM Microelectronics ...